The present disclosure relates generally to methods of manufacturing semiconductor devices and, more specifically, to methods of manufacturing a semiconductor device having an active layer spacer.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Today's fabrication plants are routinely producing devices having feature dimensions less than 90 nm. This reduction in size has helped to reduce manufacturing costs and provide greater electronic device speed and capabilities.
As device sizes shrink, the materials and processes used in fabrication must adapt to achieve more challenging specifications. One recent improvement is the adoption of silicon-on-insulator (SOI) substrates over the former industry standard of silicon substrates. SOI substrates can be generally formed by oxidizing an insulating layer formed over a handle or structural portion of a substrate. The oxidizing process may include rapid thermal processing (RTP), implantation of oxygen ions and/or other processes known to those skilled in the art. SOI substrates provide improved electrical isolation between individual devices of an integrated circuit, which allows for operation of these devices at higher cycling frequencies and faster device operating speeds. SOI substrates also provide a significant reduction in parasitic capacitance which can often lead to problems with device operation.
However, the adoption of SOI substrates has presented problems. In some applications, employing SOI substrates can lead to the contamination of device active areas. For example, wet etching processes typically employed to pattern blanket-deposited layers and to clean partially completed devices at intermediate stages of manufacture can over-etch the insulator layer of an SOI substrate, often causing undercut regions to form in the insulator layer under device gates, active regions and other patterned components. The undercut regions can accumulate residue during their formation and subsequent processing. The residue may comprise polymer resist, polysilicon, silicides, oxides and/or other processing materials. The trapped residue can contribute to transistor latch-up. The residue can also lead to pin holes and other defects in components formed over or around the undercut regions, possibly leading to excessive current leakage, threshold breakdown and/or device failure. The reliability of devices may also fall victim to these shortcomings. Moreover, such problems are exasperated as microelectronic devices experience continued scaling.
Accordingly, what is needed in the art is a microelectronics device and a method of manufacture thereof that addresses the above-discussed issues.